In electronic device implementations, it is often necessary to transfer information synchronously between different components. Such a situation may arise, for example, when transferring data between several chips or between several blocks on a chip. Because each component typically runs off of its own internal clock signal, synchronous information transfer is usually achieved by providing a reference clock signal to each of the components and then having each of the components synchronize its internal clock signal with the reference clock signal. Once synchronization is achieved, the components perform the information transfer using their own internal clock signals.
To synchronize a component's internal clock signal with a reference clock signal, a phase lock loop (PLL) is often used. A typical PLL is shown in FIG. 1, wherein the PLL 110 comprises a phase frequency detector (PFD) 112, a charge pump 114, a loop filter 116, and a voltage controlled oscillator (VCO) 118. The internally generated clock signal DCLK and the reference clock signal RCLK are fed as inputs to the PFD 112. The function of the PFD 112 is to detect the difference in phase and frequency between the two clock signals, and to generate output control signals UP and DOWN indicative of the phase and frequency differences. These control signals UP, DOWN are then fed as inputs to the charge pump 114. In response, the charge pump 114 generates a net current in accordance with the input control signals UP, DOWN, to either charge or discharge the loop filter 116 to a particular voltage. It is the voltage on loop filter 116 that controls the frequency of the DCLK generated by VCO 118. Preferably, the voltage present at the input of the VCO 118 is such that it causes the VCO 118 to generate a new DCLK signal having a frequency and phase closer to that of the reference signal RCLK- In this manner, the PLL 110 "pushes" DCLK towards RCLK.
Once the new DCLK is generated, it is fed back to the input of the PFD 112 along with RCLK, and the process is repeated Because of the feedback loop, this adjustment process continues until ideally DCLK "locks on" to RCLK in both phase and frequency. If a true lock is achieved, the PFD 112 will generate substantially identical UP and DOWN control signals (i.e. signals having substantially identical pulse widths) to indicate that there is no phase or frequency difference between the DCLK and RCLK signals. In some implementations, it is desirable for DCLK to have a frequency that is a multiple of the RCLK frequency. In such implementations, a modulo n feedback counter 120 is inserted into the feedback path as shown. If a counter 120 is used, a corresponding delay element 122 having the same delay as the counter is usually imposed between RCLK and the input of the PFD 112 to equalize signal delays.
In order for DCLK to properly lock on to RCLK, several conditions need to be met, one of which is that the charge pump needs to source and sink the same amount of current when the control signals UP, DOWN from the PFD 112 are substantially identical. Put another way, when the UP and DOWN control signals have substantially the same pulse widths, the charge pump should output a net current of substantially zero so that no further charge is injected into or removed from the loop filter, thereby maintaining the PLL 110 in locked condition. This is the ideal situation. However, because of the relatively wide range of voltages that can typically appear at the output of the charge pump 114, this ideal is very difficult to achieve.
To elaborate, there is shown in FIG. 2 a portion of a typical charge pump 114, comprising a current source 202, a current sink 216, a sourcing control 204, and a sinking control 210. The current source 202, which provides sourcing current to the output of the charge pump, is typically implemented by way of a PMOS transistor 203. The amount of sourcing current that is flowed from the current source 202 to the output of the charge pump is determined by the sourcing control 204. Typically, sourcing control 204 takes the form of a dual transistor switch comprising a first PMOS transistor 206 coupled between the current source 202 and ground, and a second PMOS transistor 208 coupled between current source 202 and the output of the charge pump. By selectively coupling the current source 202 either to ground or to the output of the charge pump in response to the control signals UP and UP' (UP' is the inverse of the UP control signal), sourcing control 204 determines the sourcing current that flows from current source 202 to the output of the charge pump.
Current sink 216 is the component in the charge pump that sinks current from the output of the charge pump. Current sink 216 is typically implemented as an NMOS transistor 217. The amount of sinking current that is flowed from the output of the charge pump to the current sink 216 is determined by the sinking control 210. Sinking control 210 is typically implemented as a dual transistor switch comprising a first NMOS transistor 212 coupled between a voltage source VDD and current sink 216, and a second NMOS transistor 214 coupled between the output of the charge pump and current sink 216. By selectively coupling the current sink 216 either to the voltage source VDD or to the output of the charge pump in response to the control signals DOWN and DOWN' (DOWN' is the inverse of the DOWN control signal), sinking control 210 determines the amount of sinking current that is flowed from the output of the charge pump to current sink 216.
The difference between the sourcing current and the sinking current is the net current that appears at the output of the charge pump. As mentioned above, when the UP and DOWN controls signals from the PFD 112 are substantially identical, the charge pump 114 should output a net current of substantially zero.
As shown in FIG. 1, the output of the charge pump 114 is fed to the loop filter 116 to charge or discharge the loop filter 116 to a particular voltage. The voltage at the loop filter 116 is then applied to the input of the VCO 118 to control the frequency of the DCLK signal generated by the VCO 118. Because the output of the charge pump 114 is coupled to the loop filter 116 which in turn is coupled to the input of the VCO 118, the output of the charge pump 114 is subjected to the same voltage range as that experienced by the input of the VCO 118. In a typical VCO, an input voltage range of 0.8 V to 2.4 V is needed to generate the necessary range of frequencies over manufacturing process, temperature, and power supply variations. With such a wide range of voltages at its output, it is difficult for the charge pump 114 to operate consistently for all possible voltages.
To illustrate this problem, suppose that a relatively low voltage (e.g. 1 V) is at the output of the charge pump 114. At this voltage, the drain to source voltage (Vds) of the sink transistor 217 (FIG. 2) is affected more than the Vds of the source transistor 203. As a result, the sinking current is decreased relative to the sourcing current, causing a net increase in sourcing current. This is so despite the fact that none of the parameters or control signals have been changed. Now, suppose that a relatively high voltage (e.g. 2.2 V) is present at the output of the charge pump 114. At this voltage, the Vds of the source transistor 203 is affected more than the Vds of the sink transistor 217. Consequently, the sourcing current is decreased relative to the sinking current, causing a net increase in sinking current. Again, no parameters or control signals have been altered. As this discussion illustrates, the charge pump 114 behaves differently for different output voltages. This phenomenon is referred to charge pump excursion. The wider the range of voltages, the more difficult it becomes to get consistent performance from the charge pump 114.
There are several known solutions to this problem, each of which has its associated drawbacks. The first possible solution is to cascode the current source 202 and the current sink 216 to increase their impedance. The higher their impedance, the less affected they will be by the voltage at the output of the charge pump. This method is effective for equalizing the direct current (DC) components of the sourcing and sinking currents; however, it does not adequately control the transient current components. The transient currents can still be affected by the gate to drain capacitance (Cgd) (which in turn is affected by the Vds) of the switches 204, 210 that control the flow of current to and from the output of the charge pump. Thus, cascoding provides only a partial solution.
Another possible solution is to implement an active loop filter 116 and a reference voltage at the output of the charge pump 114. By doing this, the voltage range at the output of the charge pump 114 can be kept small while still providing the large voltage range that is needed at the input of the VCO 118. One such loop filter 300 is shown in FIG. 3, comprising an op-amp 302 having a parallel feedback loop. One branch of the feedback loop has a capacitor 304. The other branch has a resistor 306 connected in series with a capacitor 308. At the inputs, the op-amp receives the output from the charge pump 114 and a reference voltage Vref. This loop filter 300 is effective for shielding the charge pump 114 from the wide range of voltages that can appear at the input of the VCO 118. However, in order to be implemented, it requires capacitors that do not require a certain polarity, such as poly--poly capacitors. In many less expensive manufacturing processes where only n-well capacitors are available, such capacitors cannot be fabricated. In such situations, loop filter 300 is not a practicable solution.
Another possible solution is to increase the frequency to voltage gain (.DELTA.frequency/.DELTA.Voltage) of the VCO 118 so that a smaller voltage swing will produce the same frequency change. The drawback of this solution is that it renders the VCO 118 much more sensitive to noise, thereby making the output of the VCO 118 more erratic. As the above discussion shows, none of the currently known solutions are wholly satisfactory.